1. Field of the Invention
The present invention relates generally to logic gates and more particularly to differential-signal logic gates.
2. Description of the Related Art
As stated in various logic texts (e.g., McCalla, Thomas Richard, Digital Logic and Computer Design, Macmillan Publishing, New York, 1992, p. 68), a logic variable in Boolean algebra is defined independently of any physical system. An input signal is asserted (true) when the corresponding logic variable has value 1 and an output signal is asserted (true) when a condition exists to cause the associated function to have logic value 1.
A gate is a physical circuit having at least two inputs and an output that depends on logic combinations of input signals. A positive-logic physical system assigns a high voltage level H to logic value 1 and a low voltage level L to logic value 0. In contrast, the low voltage level L is assigned to logic value 1 and the high voltage level H to logic value 0 in a negative-logic physical system. Different logic functions can, therefore, be realized by the same physical gate. In a two-input positive-logic AND gate, for example, the output has a logic value 1 only when both inputs have the logic value 1. If this same gate is used in a negative-logic system, it executes the OR logic function and the output has a logic value 1 when either input or both inputs have the logic value 1.
Accordingly, this gate is typically termed an AND/OR gate and an exemplary single-ended version is described in U.S. Pat. No. 4,007,384. Two input transistors of this gate have bases that represent gate inputs A and B. The input transistors also have first emitters that direct current steering in a differential pair and second emitters which are cross coupled to supply collector currents of the differential pair. A reference transistor has a collector coupled to an output resistor and two emitters that are also coupled to supply the differential-pair collector currents. The reference transistor's base is biased so that its emitters supply the current of the differential-pair collectors except when A and B are both high.
In high-speed operations, gates structured to use differential signals are generally preferred because comparison of oppositely-moving differential signals is more precise than the comparison of a single-ended signal to a fixed threshold level. An exemplary differential-signal gate 20 is shown in FIG. 1. The gate 20 has a first differential pair 22 of transistors 23 and 24 and the pair has a common port 25 (the pair's common emitters), first and second output ports 27 and 28 (the pair's collectors) and a differential input port 30 (the pair's bases).
The gate 20 also has a second differential pair 32 of transistors 33 and 34 and this pair has a common port 35, first and second output ports 37 and 38 and a differential input port 40. The differential pairs 22 and 32 are arranged with the output port 27 of the first differential pair 22 coupled to the common port 35 of the second differential pair 32.
A first electrical load in the form of a first resistor 44 is coupled between the first output port 37 and a voltage source 45 and a second electrical load in the form of a second resistor 46 is coupled between the voltage source 45 and the second output ports 28 and 38 of respective differential pairs 22 and 32. Buffer stages in the form of emitter followers 50 and 52 are positioned to couple the voltages at the lower ends of resistors 44 and 46 to a gate output port 54.
In accordance with conventional integrated circuit design, current sources 56, 57 and 58 are connected at one end to a voltage source 60 and respectively connected at another end to the common port 25 of the differential pair 22, the emitter of emitter follower 50 and the emitter of emitter follower 52. The gate 20 can be supplemented with a level-shifting circuit 62 so that input signals operate at the same levels. The circuit 62 couples emitter-follower transistors 64 to current sources 66 and connects their emitters 68 to the present input port 30 as indicated by broken-line arrows 69. Input signals corresponding to port 30 are then applied at the differential input port 70 and level shifted by a diode drop.
In operation of the gate 20, the first differential pair 22 steers the current of the source 56 to a path 72 (between the output port 27 and the common port 35) and steers this current to the second resistor 46 in response to respective polarities of a differential input signal at the input port 30 (i.e., a high voltage at the upper side 76 of the input port 30 steers the current to the path 72 and a low voltage at this upper side steers the current to the resistor 46). The second differential pair 32 steers the current on the path 72 to the first resistor 44 and steers this current to the second resistor 46 in response to respective polarities of a differential input signal at the input port 40.
As shown in FIG. 1, signals at the differential ports 30, 40 and 54 are respectively symbolized by symbols A, B and Q. In a positive-logic system, it is apparent that Q will always be a logic value 0 when A is a logic value 0 because this input signal causes transistor 24 to steer current to the second resistor 46 thus dropping the voltage at the upper side of the output port 54. In this condition, the logic value of B is irrelevant since there is no current on the path 72 to be steered.
The output Q will have a logic value 1 only when A and B both have a logic value 1 because only in this case is the current of the current source 56 steered (through output ports 27 and 37) to the first resistor 44 which drops the voltage at the lower side of the output port 54. It is thus apparent that the gate 20 executes the logic function Q=AB in a positive-logic system and, consequently, the logic function Q=A+B in a negative-logic system.
Although the conventional gate 20 of FIG. 1 is simple, easily fabricated and economical and thus widely used, it exhibits variations in propagation delays (i.e., time delays before the output responds to the inputs) that are sequencing dependent. In particular, the propagation delay increases (in a positive-logic system) when B has a logic value 1 and A changes from a logic value 0 to a logic value 1. In response, Q changes from a logic value 0 to a logic value 1 but with an increased propagation delay compared to other input sequences.
Even small propagation-delay variations (e.g., .about.20 picoseconds) can cause signal degradation in integrated-circuit gates that are operated at high-speed (e.g., &gt;1 GHz) in applications (e.g., automatic test equipment) that demand high fidelity in signal parameters (e.g., signal timing, signal levels, and signal transitions).